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124 lines
4.8 KiB
124 lines
4.8 KiB
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<a name="introducing"><!-- --></a>
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<h1 class="topictitle1">Introducing Intel® Threading Building Blocks</h1>
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<div>
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<div class="section">
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<p>Intel® Threading Building Blocks (Intel® TBB) is a
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library that supports scalable parallel programming using standard ISO C++
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code. It does not require special languages or compilers. It is designed to
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promote scalable data parallel programming. Additionally, it fully supports
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nested parallelism, so you can build larger parallel components from smaller
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parallel components. To use the library, you specify tasks, not threads, and
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let the library map tasks onto threads in an efficient manner.
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</p>
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<p>Many of the library interfaces employ generic
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programming, in which interfaces are defined by requirements on types and not
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specific types. The C++ Standard Template Library (STL) is an example of
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generic programming. Generic programming enables Intel® Threading Building
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Blocks to be flexible yet efficient. The generic interfaces enable you to
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customize components to your specific needs.
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</p>
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<p>The net result is that Intel® Threading Building
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Blocks enables you to specify parallelism far more conveniently than using raw
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threads, and at the same time can improve performance.
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</p>
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<p>This document is a reference manual. It is
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organized for looking up details about syntax and semantics. You should first
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read the
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<em>Intel® Threading Building Blocks Getting Started Guide</em> and the
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<em>Intel® Threading Building Blocks Tutorial</em> to learn how to use
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the library effectively. The
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<em>Intel® Threading Building Blocks Design Patterns</em> document is
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another useful resource.
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</p>
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<div class="Note"><h3 class="NoteTipHead">
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Tip</h3>
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<p>Even experienced parallel programmers should read
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the
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<em>Intel® Threading Building Blocks Tutorial</em> before using this
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reference guide because Intel® Threading Building Blocks uses a surprising
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recursive model of parallelism and generic algorithms.
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</p>
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</div>
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</div>
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<p>
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<div class="tablenoborder"><table cellpadding="4" summary="" frame="border" border="1" cellspacing="0" rules="all">
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<thead align="left">
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<tr>
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<th class="cellrowborder" align="left" valign="top" width="100%" id="d90964e74">
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<p>Optimization Notice
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</p>
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</th>
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</tr>
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</thead>
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<tbody>
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<tr>
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<td class="bgcolor(#ccecff)" bgcolor="#ccecff" valign="top" width="100%" headers="d90964e74 ">
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Intel's compilers may or may not optimize to the same degree for non-Intel
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microprocessors for optimizations that are not unique to Intel microprocessors.
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These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other
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optimizations. Intel does not guarantee the availability, functionality, or
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effectiveness of any optimization on microprocessors not manufactured by Intel.
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Microprocessor-dependent optimizations in this product are intended for use
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with Intel microprocessors. Certain optimizations not specific to Intel
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microarchitecture are reserved for Intel microprocessors. Please refer to the
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applicable product User and Reference Guides for more information regarding the
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specific instruction sets covered by this notice.
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<p>Notice revision #20110804
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</p>
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</td>
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</tr>
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</tbody>
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</table>
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</div>
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</p>
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</div>
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</body>
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</html>
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