Intel® Threading Building Blocks (Intel® TBB) is a library that supports scalable parallel programming using standard ISO C++ code. It does not require special languages or compilers. It is designed to promote scalable data parallel programming. Additionally, it fully supports nested parallelism, so you can build larger parallel components from smaller parallel components. To use the library, you specify tasks, not threads, and let the library map tasks onto threads in an efficient manner.
Many of the library interfaces employ generic programming, in which interfaces are defined by requirements on types and not specific types. The C++ Standard Template Library (STL) is an example of generic programming. Generic programming enables Intel® Threading Building Blocks to be flexible yet efficient. The generic interfaces enable you to customize components to your specific needs.
The net result is that Intel® Threading Building Blocks enables you to specify parallelism far more conveniently than using raw threads, and at the same time can improve performance.
This document is a reference manual. It is organized for looking up details about syntax and semantics. You should first read the Intel® Threading Building Blocks Getting Started Guide and the Intel® Threading Building Blocks Tutorial to learn how to use the library effectively. The Intel® Threading Building Blocks Design Patterns document is another useful resource.
Even experienced parallel programmers should read the Intel® Threading Building Blocks Tutorial before using this reference guide because Intel® Threading Building Blocks uses a surprising recursive model of parallelism and generic algorithms.
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Optimization Notice |
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Intel's compilers may or may not optimize to the same degree for non-Intel
microprocessors for optimizations that are not unique to Intel microprocessors.
These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other
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effectiveness of any optimization on microprocessors not manufactured by Intel.
Microprocessor-dependent optimizations in this product are intended for use
with Intel microprocessors. Certain optimizations not specific to Intel
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specific instruction sets covered by this notice.
Notice revision #20110804 |