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  27. <h1 class="topictitle1">Introducing Intel&reg; Threading Building Blocks</h1>
  28. <div>
  29. <p>Intel&reg; Threading Building Blocks (Intel&reg; TBB) is a
  30. library that supports scalable parallel programming using standard ISO C++
  31. code. It does not require special languages or compilers. It is designed to
  32. promote scalable data parallel programming. Additionally, it fully supports
  33. nested parallelism, so you can build larger parallel components from smaller
  34. parallel components. To use the library, you specify tasks, not threads, and
  35. let the library map tasks onto threads in an efficient manner.
  36. </p>
  37. <p>Many of the library interfaces employ generic
  38. programming, in which interfaces are defined by requirements on types and not
  39. specific types. The C++ Standard Template Library (STL) is an example of
  40. generic programming. Generic programming enables Intel&reg; TBB to be flexible yet
  41. efficient. The generic interfaces enable you to customize components to your
  42. specific needs.
  43. </p>
  44. <p>The net result is that Intel&reg; TBB enables you to
  45. specify parallelism far more conveniently than using raw threads, and at the
  46. same time can improve performance.
  47. </p>
  48. <p>
  49. <div class="tablenoborder"><table cellpadding="4" summary="" frame="border" border="1" cellspacing="0" rules="all">
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  51. <tr>
  52. <th class="cellrowborder" align="left" valign="top" width="100%" id="d608e50">
  53. <p>Optimization Notice
  54. </p>
  55. </th>
  56. </tr>
  57. </thead>
  58. <tbody>
  59. <tr>
  60. <td class="bgcolor(#ccecff)" bgcolor="#ccecff" valign="top" width="100%" headers="d608e50 ">
  61. Intel's compilers may or may not optimize to the same degree for non-Intel
  62. microprocessors for optimizations that are not unique to Intel microprocessors.
  63. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other
  64. optimizations. Intel does not guarantee the availability, functionality, or
  65. effectiveness of any optimization on microprocessors not manufactured by Intel.
  66. Microprocessor-dependent optimizations in this product are intended for use
  67. with Intel microprocessors. Certain optimizations not specific to Intel
  68. microarchitecture are reserved for Intel microprocessors. Please refer to the
  69. applicable product User and Reference Guides for more information regarding the
  70. specific instruction sets covered by this notice.
  71. <p>Notice revision #20110804
  72. </p>
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  74. </tr>
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  76. </table>
  77. </div>
  78. </p>
  79. </div>
  80. <div class="familylinks">
  81. <div class="parentlink"><strong>Parent topic:</strong>&nbsp;<a href="../main/title.htm">Intel&reg; Threading Building Blocks Documentation</a></div>
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