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@ -439,7 +439,7 @@ inline uint32 mulu32_unchecked (uint32 arg1, uint32 arg2) |
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__asm__ __volatile__ ( \ |
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__asm__ __volatile__ ( \ |
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"wr %%g0,%%g0,%%y\n\t" \ |
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"wr %%g0,%%g0,%%y\n\t" \ |
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"udiv %2,%3,%0\n\t" \ |
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"udiv %2,%3,%0\n\t" \ |
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"umul %0,%3,%1" \ |
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"umul %0,%3,%1\n\t" \ |
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"sub %2,%1,%1" \ |
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"sub %2,%1,%1" \ |
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: "=&r" (__q), "=&r" (__r) \ |
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: "=&r" (__q), "=&r" (__r) \ |
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: "r" (__x), "r" (__y)); \ |
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: "r" (__x), "r" (__y)); \ |
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@ -528,7 +528,7 @@ inline uint32 mulu32_unchecked (uint32 arg1, uint32 arg2) |
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__asm__ __volatile__ ( \ |
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__asm__ __volatile__ ( \ |
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"wr %%g0,%%g0,%%y\n\t" \ |
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"wr %%g0,%%g0,%%y\n\t" \ |
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"udiv %2,%3,%0\n\t" \ |
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"udiv %2,%3,%0\n\t" \ |
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"umul %0,%3,%1" \ |
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"umul %0,%3,%1\n\t" \ |
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"sub %2,%1,%1" \ |
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"sub %2,%1,%1" \ |
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: "=&r" (__q), "=&r" (__r) \ |
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: "=&r" (__q), "=&r" (__r) \ |
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: "r" (__x), "r" (__y)); \ |
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: "r" (__x), "r" (__y)); \ |
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@ -578,7 +578,7 @@ inline uint32 mulu32_unchecked (uint32 arg1, uint32 arg2) |
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__asm__ __volatile__ ( \ |
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__asm__ __volatile__ ( \ |
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"wr %%g0,%%g0,%%y\n\t" \ |
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"wr %%g0,%%g0,%%y\n\t" \ |
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"udiv %2,%3,%0\n\t" \ |
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"udiv %2,%3,%0\n\t" \ |
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"umul %0,%3,%1" \ |
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"umul %0,%3,%1\n\t" \ |
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"sub %2,%1,%1" \ |
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"sub %2,%1,%1" \ |
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: "=&r" (__q), "=&r" (__r) \ |
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: "=&r" (__q), "=&r" (__r) \ |
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: "r" (__x), "r" (__y)); \ |
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: "r" (__x), "r" (__y)); \ |
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@ -690,7 +690,7 @@ inline uint32 mulu32_unchecked (uint32 arg1, uint32 arg2) |
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__asm__ __volatile__ ( \ |
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__asm__ __volatile__ ( \ |
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"wr %2,%%g0,%%y\n\t" \ |
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"wr %2,%%g0,%%y\n\t" \ |
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"udiv %3,%4,%0\n\t" \ |
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"udiv %3,%4,%0\n\t" \ |
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"umul %0,%4,%1" \ |
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"umul %0,%4,%1\n\t" \ |
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"sub %3,%1,%1" \ |
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"sub %3,%1,%1" \ |
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: "=&r" (__q), "=&r" (__r) \ |
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: "=&r" (__q), "=&r" (__r) \ |
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: "r" (__xhi), "r" (__xlo), "r" (__y)); \ |
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: "r" (__xhi), "r" (__xlo), "r" (__y)); \ |
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@ -791,7 +791,7 @@ inline uint32 mulu32_unchecked (uint32 arg1, uint32 arg2) |
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__asm__ __volatile__ ( \ |
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__asm__ __volatile__ ( \ |
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"wr %2,%%g0,%%y\n\t" \ |
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"wr %2,%%g0,%%y\n\t" \ |
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"udiv %3,%4,%0\n\t" \ |
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"udiv %3,%4,%0\n\t" \ |
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"umul %0,%4,%1" \ |
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"umul %0,%4,%1\n\t" \ |
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"sub %3,%1,%1" \ |
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"sub %3,%1,%1" \ |
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: "=&r" (__q), "=&r" (__r) \ |
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: "=&r" (__q), "=&r" (__r) \ |
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: "r" (__xhi), "r" (__xlo), "r" (__y)); \ |
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: "r" (__xhi), "r" (__xlo), "r" (__y)); \ |
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