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170 lines
5.4 KiB
170 lines
5.4 KiB
// firewire protocol with integer semantics
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// dxp/gxn 14/06/01
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// CLOCKS
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// x1 (x2) clock for node1 (node2)
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// y1 and y2 (z1 and z2) clocks for wire12 (wire21)
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mdp
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// maximum and minimum delays
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// fast
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const int rc_fast_max = 85;
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const int rc_fast_min = 76;
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// slow
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const int rc_slow_max = 167;
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const int rc_slow_min = 159;
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// delay caused by the wire length
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const int delay = 3;
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// probability of choosing fast
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const double fast = 0.5;
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const double slow=1-fast;
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module wire12
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// local state
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w12 : [0..9];
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// 0 - empty
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// 1 - rec_req
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// 2 - rec_req_ack
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// 3 - rec_ack
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// 4 - rec_ack_idle
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// 5 - rec_idle
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// 6 - rec_idle_req
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// 7 - rec_ack_req
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// 8 - rec_req_idle
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// 9 - rec_idle_ack
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// clock for wire12
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y1 : [0..delay+1];
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y2 : [0..delay+1];
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// empty
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// do not need y1 and y2 to increase as always reset when this state is left
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// similarly can reset y1 and y2 when we re-enter this state
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[snd_req12] w12=0 -> (w12'=1) & (y1'=0) & (y2'=0);
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[snd_ack12] w12=0 -> (w12'=3) & (y1'=0) & (y2'=0);
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[snd_idle12] w12=0 -> (w12'=5) & (y1'=0) & (y2'=0);
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[time] w12=0 -> (w12'=w12);
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// rec_req
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[snd_req12] w12=1 -> (w12'=1);
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[rec_req12] w12=1 -> (w12'=0) & (y1'=0) & (y2'=0);
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[snd_ack12] w12=1 -> (w12'=2) & (y2'=0);
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[snd_idle12] w12=1 -> (w12'=8) & (y2'=0);
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[time] w12=1 & y2<delay -> (y1'=min(y1+1,delay+1)) & (y2'=min(y2+1,delay+1));
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// rec_req_ack
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[snd_ack12] w12=2 -> (w12'=2);
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[rec_req12] w12=2 -> (w12'=3);
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[time] w12=2 & y1<delay -> (y1'=min(y1+1,delay+1)) & (y2'=min(y2+1,delay+1));
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// rec_ack
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[snd_ack12] w12=3 -> (w12'=3);
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[rec_ack12] w12=3 -> (w12'=0) & (y1'=0) & (y2'=0);
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[snd_idle12] w12=3 -> (w12'=4) & (y2'=0);
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[snd_req12] w12=3 -> (w12'=7) & (y2'=0);
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[time] w12=3 & y2<delay -> (y1'=min(y1+1,delay+1)) & (y2'=min(y2+1,delay+1));
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// rec_ack_idle
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[snd_idle12] w12=4 -> (w12'=4);
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[rec_ack12] w12=4 -> (w12'=5);
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[time] w12=4 & y1<delay -> (y1'=min(y1+1,delay+1)) & (y2'=min(y2+1,delay+1));
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// rec_idle
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[snd_idle12] w12=5 -> (w12'=5);
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[rec_idle12] w12=5 -> (w12'=0) & (y1'=0) & (y2'=0);
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[snd_req12] w12=5 -> (w12'=6) & (y2'=0);
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[snd_ack12] w12=5 -> (w12'=9) & (y2'=0);
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[time] w12=5 & y2<delay -> (y1'=min(y1+1,delay+1)) & (y2'=min(y2+1,delay+1));
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// rec_idle_req
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[snd_req12] w12=6 -> (w12'=6);
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[rec_idle12] w12=6 -> (w12'=1);
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[time] w12=6 & y1<delay -> (y1'=min(y1+1,delay+1)) & (y2'=min(y2+1,delay+1));
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// rec_ack_req
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[snd_req12] w12=7 -> (w12'=7);
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[rec_ack12] w12=7 -> (w12'=1);
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[time] w12=7 & y1<delay -> (y1'=min(y1+1,delay+1)) & (y2'=min(y2+1,delay+1));
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// rec_req_idle
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[snd_idle12] w12=8 -> (w12'=8);
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[rec_req12] w12=8 -> (w12'=5);
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[time] w12=8 & y1<delay -> (y1'=min(y1+1,delay+1)) & (y2'=min(y2+1,delay+1));
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// rec_idle_ack
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[snd_ack12] w12=9 -> (w12'=9);
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[rec_idle12] w12=9 -> (w12'=3);
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[time] w12=9 & y1<delay -> (y1'=min(y1+1,delay+1)) & (y2'=min(y2+1,delay+1));
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endmodule
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module node1
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// clock for node1
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x1 : [0..168];
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// local state
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s1 : [0..8];
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// 0 - root contention
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// 1 - rec_idle
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// 2 - rec_req_fast
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// 3 - rec_req_slow
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// 4 - rec_idle_fast
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// 5 - rec_idle_slow
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// 6 - snd_req
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// 7- almost_root
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// 8 - almost_child
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// added resets to x1 when not considered again until after rest
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// removed root and child (using almost root and almost child)
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// root contention immediate state)
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[snd_idle12] s1=0 -> fast : (s1'=2) & (x1'=0) + slow : (s1'=3) & (x1'=0);
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[rec_idle21] s1=0 -> (s1'=1);
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// rec_idle immediate state)
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[snd_idle12] s1=1 -> fast : (s1'=4) & (x1'=0) + slow : (s1'=5) & (x1'=0);
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[rec_req21] s1=1 -> (s1'=0);
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// rec_req_fast
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[rec_idle21] s1=2 -> (s1'=4);
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[snd_ack12] s1=2 & x1>=rc_fast_min -> (s1'=7) & (x1'=0);
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[time] s1=2 & x1<rc_fast_max -> (x1'=min(x1+1,168));
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// rec_req_slow
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[rec_idle21] s1=3 -> (s1'=5);
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[snd_ack12] s1=3 & x1>=rc_slow_min -> (s1'=7) & (x1'=0);
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[time] s1=3 & x1<rc_slow_max -> (x1'=min(x1+1,168));
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// rec_idle_fast
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[rec_req21] s1=4 -> (s1'=2);
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[snd_req12] s1=4 & x1>=rc_fast_min -> (s1'=6) & (x1'=0);
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[time] s1=4 & x1<rc_fast_max -> (x1'=min(x1+1,168));
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// rec_idle_slow
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[rec_req21] s1=5 -> (s1'=3);
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[snd_req12] s1=5 & x1>=rc_slow_min -> (s1'=6) & (x1'=0);
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[time] s1=5 & x1<rc_slow_max -> (x1'=min(x1+1,168));
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// snd_req
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// do not use x1 until reset (in state 0 or in state 1) so do not need to increase x1
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// also can set x1 to 0 upon entering this state
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[rec_req21] s1=6 -> (s1'=0);
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[rec_ack21] s1=6 -> (s1'=8);
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[time] s1=6 -> (s1'=s1);
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// almost root (immediate)
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// loop in final states to remove deadlock
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[] s1=7 & s2=8 -> (s1'=s1);
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[] s1=8 & s2=7 -> (s1'=s1);
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[time] s1=7 -> (s1'=s1);
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[time] s1=8 -> (s1'=s1);
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endmodule
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// construct remaining automata through renaming
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module wire21=wire12[w12=w21, y1=z1, y2=z2,
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snd_req12=snd_req21, snd_idle12=snd_idle21, snd_ack12=snd_ack21,
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rec_req12=rec_req21, rec_idle12=rec_idle21, rec_ack12=rec_ack21]
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endmodule
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module node2=node1[s1=s2, s2=s1, x1=x2,
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rec_req21=rec_req12, rec_idle21=rec_idle12, rec_ack21=rec_ack12,
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snd_req12=snd_req21, snd_idle12=snd_idle21, snd_ack12=snd_ack21]
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endmodule
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// reward structures
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// time
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rewards "time"
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[time] true : 1;
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endrewards
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// time nodes sending
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rewards "time_sending"
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[time] (w12>0 | w21>0) : 1;
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endrewards
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label "elected" = ((s1=8) & (s2=7)) | ((s1=7) & (s2=8));
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